1. Field of the Invention
The present invention relates to a circuit board and in more detail to a circuit board with a multilayer structure constructed by laminating a core layer and one or more wiring layers.
2. Related Art
In recent years, in response to demand for improved performance and miniaturization of electronic appliances, there have been rapid increases in the packing density of electronic components in electronic appliances. As the packing density has increased, it has become common for semiconductor chips to be surface-mounted on circuit boards as bare chips, a process called “flip-chip mounting”.
However, when flip-chip mounting is carried out, although the thermal expansion coefficient in the planar direction for a semiconductor chip produced using a typical semiconductor material is around 3.5 ppm/° C., the thermal expansion coefficient in the planar direction for a typical circuit board that uses a glass epoxy substrate as a core substrate is 12 to 20 ppm/° C., resulting in a relatively large difference in thermal expansion coefficients. This means that changes in environmental temperature and the like are likely to produce stress at the electrical connections between the circuit board and the semiconductor chip. The production of such stress can cause cracking or delamination at the connections.
As one method of eliminating or reducing the above problem due to the difference in thermal expansion coefficients in the planar direction between the circuit board and the semiconductor chip, it would be conceivable to use a circuit board with a low thermal expansion coefficient.
One example of a conventional circuit board with a reduced thermal expansion coefficient is the circuit board 100 disclosed in Patent Document 1. As shown in the detailed cross-sectional view in FIG. 5, the plan view in FIG. 6A and the schematic cross-sectional view in FIG. 6B, the circuit board 100 includes a core layer 110 composed of a carbon fiber material 111a and a resin composite 111b that includes an inorganic filler, laminated wiring portions 120 that each include insulating layers 121 formed on the core layer 110 and wiring patterns 122 provided on the insulating layers 121, and conductive portions 130 that extend in the thickness direction inside the core layer 110 and electrically connect the wiring patterns 122 of the laminated wiring portions 120. By using this construction, it is possible to sufficiently reduce the thermal expansion coefficient in the planar direction of the circuit board.
Patent Document 1
    Japanese Laid-Open Patent Publication No. 2004-119691